An electrostatic discharge (ESD) is a sudden unwanted current that can flow between two objects at different electrical potentials and as a result cause damage to electronic equipment that constitutes one or other of the two objects. ESD is a serious issue in solid-state electronics and can cause immediate permanent damage to a circuit or can result in less obvious forms of degradation that may affect the long-term reliability and performance of the circuit. As a result, there are many methods, systems and circuits for preventing an ESD event. The ESD prevention can form part of the circuit or device or can constitute an external protection component located within the circuit layout.
In order to determine the susceptibility of an electronic circuit to an ESD event, there are a number of ESD test models which exist and which specify the nature of an ESD event. The models are defined by various standards and the most common models include the human body model (HBM), the gun stress model (GSM) and the machine model (MM).
The gun or machine model ESD event as specified in International Electronics Commission (IEC), standard 61000-4-2 and Joint Election Device Engineering Course JESD22-A115A respectively, deal with situations where the ESD injected current may be high. The table below shows the situation for contact discharge and air discharge and sets out a level to which the equipment specification should comply and required test voltage associated with each level. The standard ESD gun test current waveform is shown in FIG. 1.
1a - Contact discharge1b - Air dischargeTest voltageTest voltageLevelkVLevelkV1212242436384842x1)Specialx1)Special1)“x” is an open level. The level has to be specified in the dedicated equipment specification. From IEC 61000-4-2 if higher voltages than those shown are specified, special test equipment may be needed.
Standard prior art protection circuits protect integrated circuits (IC) by means of voltage clamps combined with diodes or PNP transistors connected to the input and output (I/O) pins. These protection circuits divert the current that is being injected during an ESD event by essentially clamping the IC pin voltage at a level that is sufficient to avoid circuit destruction. However, when large sized power transistors, with low ohmic routing, connect to an input/output (I/O) pin, an ESD event can cause a fast voltage transient (high dV/dt event) which results in either the base or gate of the power transistor being pulled up through a parasitic base collector or drain gate capacitance, allowing the power transistor to switch on. Even though the pin voltage is clamped and stays below the transistor breakdown voltage, the power transistor current resulting from this could easily result in device destruction if the ESD injected current is sufficiently high, such as might be experienced during an ESD gun or machine model event.
FIG. 2 shows an example of a prior art drawing showing a bipolar transistor ESD protection circuit which includes three input/output (I/O) pins 200, 202, 204; three diodes 206, 208, 210 and a voltage clamp 212.
US2006/0043490A1 discloses a system and method for the protection of a transistor from electrostatic discharge current associated with an ESD event. This is achieved by implementing an ESD detector circuit which is separate from the main clamp circuit and which detects an ESD event by detecting a high dV/dt event using an RC time constant and capacitive coupling. However, it is necessary to optimise the RC time constant for a particular ESD model event and in the case where inductive loads are switched, the ESD detect circuit can be triggered during normal operation.